`define DELAY(N, clk) begin \
	repeat(N) @(posedge clk);\
	#1ps;\
end

module testbench();

//-------------------------------------{{{common cfg
timeunit 1ns;
timeprecision 1ps;
initial $timeformat(-9,3,"ns",6);

string tc_name;
int tc_seed;

initial begin
    if(!$value$plusargs("tc_name=%s", tc_name)) $error("no tc_name!");
    else $display("tc name = %0s", tc_name);
    if(!$value$plusargs("ntb_random_seed=%0d", tc_seed)) $error("no tc_seed");
    else $display("tc seed = %0d", tc_seed);
end
//-------------------------------------}}}

//-------------------------------------{{{parameter declare
parameter WIDTH = 4;
//-------------------------------------}}}

//-------------------------------------{{{signal declare
logic [WIDTH -1:0] binary;
logic [WIDTH -1:0] gray;
logic clk, rst_n;
//-------------------------------------}}}

//-------------------------------------{{{clk/rst cfg
initial forever #5ns clk = ~clk;
initial begin
    rst_n = 1'b0;
	`DELAY(30, clk);
	rst_n = 1'b1;
end
initial begin
    #100000ns $finish;
end
//-------------------------------------}}}

//-------------------------------------{{{valid sig assign
//-------------------------------------}}}

//-------------------------------------{{{ready sig assign
//-------------------------------------}}}

//-------------------------------------{{{data  sig assign

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        gray <= 4'b0;
    end 
    else begin
        gray <= $urandom;
    end
end
//-------------------------------------}}}

//-------------------------------------{{{other sig assign
initial begin
    `DELAY(50, clk);
end

//-------------------------------------}}}

//-------------------------------------{{{rtl inst
async_fifo_g2b_unit #(
    .WIDTH(WIDTH)) 
u_async_fifo_g2b_unit(
    .binary(binary),
    .gray(gray)
);
//-------------------------------------}}}

endmodule
